1. Field of the Invention
The present invention relates to a method of fabricating a FLASH memory device, and more particularly to a method of fabricating a FLASH memory device including a split gate.
2. Discussion of Related Art
FLASH memory devices can electrically write or erase data. FLASH memory devices maintain data without a power supply. Therefore, the FLASH memory devices have been widely used in various technologies. FLASH memory devices can be classified into NAND type and NOR type devices according to a structure of a memory cell array. Comparatively, NAND type FLASH memory devices can be highly integrated within a unit area of a circuit and NOR type FLASH memory devices have a fast response speed.
In NOR type FLASH memory devices, memory cells are arranged along rows and columns, a plurality of bit lines are disposed parallel to the rows and a plurality of word lines are disposed with parallel to columns. The memory cells in each of the rows are connected to a bit line in parallel and the memory cells in each of the columns are connected to a word line in parallel.
A memory cell of a NOR type FLASH memory device is selected by selecting a word line and a bit line. Accordingly, the memory cells of NOR type FLASH memory devices can be accessed randomly, so that the response speed thereof is faster than that of the NAND type FLASH memory device. In the NOR type FLASH memory device, a plurality of memory cells are connected to a bit line in parallel, so that if a memory cell transistor connected to the bit line is erased, current passes through the bit line regardless of a state of a selected memory cell. Therefore, each memory cell that is connected to the bit line is read as if the memory cells are in a turned-on state.
A split gate type FLASH memory device is another type of FLASH memory device. Word lines of the split gate type FLASH memory device act as a selection gate and a control gate, overlap a portion of a floating gate.
FIG. 1A is a top plane view of a conventional split gate type FLASH memory device.
Referring to FIG. 1A, device isolation layers 8 are disposed to defined first and second active regions 12a and 12b, which intersect each other. A pair of floating gate patterns 14 are disposed on each first active region 12a between adjacent second active regions 12b. Word lines 18 crossing over the first active regions 12a are disposed on the floating gate patterns 14. The word lines 18 lie on top of the floating gate patterns 14 and on the first active regions 12a beside a sidewall of the floating gate patterns 14. Drain regions are formed in the first active regions 12a between adjacent word lines 18 and a bit line plug 20 is connected to each drain region.
Referring to FIG. 1B, after active regions 12a and 12b are defined in a substrate, a conductive layer is formed. The conductive layer is patterned to form a floating gate 14 of the conventional split gate type nonvolatile memory device. Edges of a pattern formed by a photolithographic process are rounded due to a proximity effect even though the pattern is designed to be rectangular in layout. As illustrated in the FIG. 1B, a width of the elliptical floating gate pattern may reduced at the edges, so that when the floating gate pattern is misaligned, a channel under the floating gate decreases in width and influences characteristics of the memory cell. Thus, variations in cell characteristics in a cell array may be widened. Referring to FIG. 1C, if a width of the active region becomes narrow due to a high integration of the semiconductor device, a misalignment of the floating gate causes a direct contact of a word line 18 and a substrate 10 between a device isolation layer 8 and the floating gate pattern 14. In addition, the floating gates of the adjoining memory cells connected to adjoining bit lines needs to be separated from each other on the device isolation layer by a predetermined distance, so that the distance between the adjoining floating gates should be defined wider than a minimum line width. Therefore, the width of the device isolation pattern 8 may not be reduced to a minimum line width.